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tda7310 serial bus controlled audio processor input multiplexer: - 4 stereo inputs - one differential stereo input for remote sources selectable input gain for optimal adaption to different sources input and output for external equalizer or noise reduction sys- tem volume control in 1.25db steps loudness function treble and bass control four speaker attenuators: - 4 independent speakers control in 1.25db steps for balance and fader facilities - independent mute function all functions programmable via se- rial bus selectable chip address dedicated pin description the tda7310 is a volume, tone (bass and treble) and fader (front/rear) processor for high quality audio applications in car radio and hi-fi systems. loudness and selectable input gain are provided. the control of all fuctions is accomplished by serial bus microprocessor interface. the ac signal setting is obtained by resistor networks and switches combined with operational amplifiers. thanks to the used bipolar/cmos tecnology, low distortion, low noise and dc stepping are ob- tained. this is advanced information on a new product now in development or undergoing evaluation. details are subject to change withou t notice. november 1999 ? pqfp44 (10 x 10) ordering number: tda7310 pin connection (top view) 1/15
thermal data symbol description value unit r th j-pins thermal resistance junction-pins max 85 c/w quick reference data symbol parameter min. typ. max. unit v s supply voltage 6 9 10 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 % s/n signal to noise ratio 106 db s c channel separation f = 1khz 103 db volume control 1.25db step -78.75 0 db bass and treble control 2db step -14 +14 db fader and balance control 1.25db step -38.75 0 db input gain 6.25db step 0 18.75 db mute attenuation 100 db absolute maximum ratings symbol parameter value unit v s operating supply voltage 10.2 v t amb ambient temperature -40 to 85 c t stg storage temperature range -55 to +150 c test circuit tda7310 2/15
l1 28 l1 l2 27 l2 l3 26 l3 l4 25 l4 l5 16 l5 input selector + gain c1 c2 c3 c4 c5 left inputs cd 4x 2.2 m f 4.7 m f r5 17 supply sgnd 10 m f c6 18 r5 r4 19 r4 r3 20 r3 r2 21 r2 24 r1 c7 c8 c9 c10 c11 4x 2.2 m f r1 4.7 m f right inputs 897 v cc agnd cref c14 2.2 m f out(l) in(l) 30 29 vol + loud loud sw 38 39 c16 100nf 100nf bass loud(l) c19 32 5.6k r2 bout(l) 31 bin(l) c20 100nf rb treble c22 2.7nf treble(l) 10 mute d94au170 mute serial bus decoder + latches spkr att spkr att 2 42 vol + loud bass treble out(r) in(r) c13 2.2 m f 15 14 40 c15 loud(r) 100nf 100nf 100nf c17 c18 5.6k r1 bout(r) bin(r) 36 35 rb c21 2.7nf treble(r) mute spkr att mute spkr att 50k 37 6 5 4 3 43 41 addr scl sen sda diggnd bus out right front out right rear +v cc out left rear out left front 13 22 m f c12 block diagram tda7310 3/15
electrical characteristics (t amb = 25c, v s = 9v, r l = 10k w , r g = 600 w , g v =0db, f = 1khz unless otherwise specified) (refer to the test circuit) symbol parameter test condition min. typ. max. unit supply v s supply voltage 6 9 10 v i s supply current 4 8 11 ma svr ripple rejection 60 85 db input selectors r ii input resistance input 1, 2, 3, 4 50 k w differential input 10 k w v cl clipping level 2 2.5 vrms cmrr common mode rejection differential input 65 db ins input separation (2) 80 100 db r l output load resistance 2 k w g inmin min. input gain -1 0 1 db g inmax max. input gain 18.75 db g step step resolution 6.25 db e in input noise g = 18.75db 2 m v v dc dc steps adjacent gain steps 4 mv g = 18.75 to mute 4 mv volume control r in input resistance 33 k w c range control range 75 db a vmin min. attenuation -1 0 1 db a vmax max. attenuation 75 db a step step resolution 1.25 db e a attenuation set error a v = 0 to -20db a v = -20 to -60db -1.25 -3 0 1.25 2 db db e t tracking error 2db v dc dc steps adjacent attenuation steps from 0db to a vmax 0.1 0.5 mv mv speaker attenuators control range 37.5 db step resolution 1.25 db attenuation set error 1.5 db output mute attenuation 80 100 db dc steps adjacent att. steps from 0 to mute 0 1 mv mv bass control (1) control range +14 db step resolution 2 db r b internal feedback resistance 50 k w v dc dc steps adjacent control steps 0.1 mv tda7310 4/15
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit treble control (1) control range +14 db step resolution 2 db v dc dc steps adjacent control steps 0.1 mv audio outputs clipping level d = 0.3% 2.5 vrms output load resistance 2 k w output load capacitance 10 nf output resistance 75 120 w dc voltage level 4.2 4.5 4.8 v general e no output noise bw = 20-20khz, flat output muted all gains = 0db 2.5 515 m v m v s/n signal to noise ratio all gains = 0db; v o = 1vrms 106 db d distortion v in = 1vrms 0.01 % sc channel separation left/right 80 103 db total tracking error a v = 0 to -20db -20 to -60 db 0 0 1 2 db db bus inputs v il input low voltage 1 v v ih input high voltage 3 v v o output voltage sda acknowledge i o = 1.6ma 0.4 v loudness switch v il input low voltage 1 v v ih input high voltage 3 v i in input current -5 +5 m a dc step on ? ? off position 0.1 mv loudness off = pin38 open; loudness on = pin 38 closed to gnd address pin (internal 50k w pull down resistor) v il input low voltage 1 v v ih input high voltage v cc -1v v i in input current m a notes: (1) bass and treble response see attached diagram (fig.17). the center frequency and quality of the resonance behaviour can be choosen by the external circuitry. a standard first order bass response can be realized by a standard feedback network (2) the selected input is grounded thru the 2.2 m f capacitor. tda7310 5/15
application suggestion (see to test circuit) component recc. value purpose smaller than r ecc. value larger than c1 to c4, c8 to c11 2.2 m f thd optimization at low frequencies worse thd at very low frequencies c5, c7 c6 4.7 m f 10 m f cmrr optimization differential input worse cmrr for ratio not equal to 1 2 c12 22 m fc ref svr optimization < -66 db better svr at low frequencies worse svr at low frequencies c13, c14 2.2 m f decoupling input-output if external equalizer is not used c15, c16 100nf loudness characteristic c17, c18 r1 c!9, c20 r2 100nf 5.6k w 100nf 5.6k w bass filter (standard t - type) cut freq. = 100hz c21 c22 2.7nf treble filter higher cut frequency lower cut frequency figure 1: loudness versus volume attenuation figure 2: loudness versus frequency (c loud = 100nf) tda7310 6/15
figure 3: loudness versus external capacitors loudness v s = 9v volume = -40db all other control flat c in = 2.2 m f figure 4: noise vs. volume/gain settings figure 5: signal to noise ratio vs. volume setting figure 6: distortion vs. load resistance tda7310 7/15
figure 8 : input separation (l1 ? l2, l3, l4) vs. frequency figure 7 : channel separation (l ? r) vs. frequency figure 9 : supply voltage rejection vs. frequency figure 10: output clipping level vs. supply voltage tda7310 8/15
figure 12: supply current vs. temperature figure 14: typical tone response (with the ext. components indicated in the test circuit) figure 11: quiescent current vs. supply voltage figure 13: bass resistance vs. temperature tda7310 9/15
figure 15: data validity on the i 2 cbus figure 17: acknowledge on the i 2 cbus application information (continued) serial bus interface s-bus interface and i 2 cbus compability data transmission from microprocessor to the tda7310 and viceversa takes place thru the 3- wire s-bus interface, consisting of the three lines sda, scl, sen. if sda and sen inputs are short-circuited together, then the tda7310 ap- pears as a standard i 2 cbus slave. according to i 2 cbus specification the s-bus lines are connected to a positive supply voltage via pull-up resistors. data validity as shown in fig. 15, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions i 2 cbus: as shown in fig. 16 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high tran- sition of the sda line while scl is high. s-bus: the start/stop conditions (points 1 and 6) are de- tected exclusively by a transition of the sen line (1 ? 0 / 0 ? 1)wile the scl line is at the high level. the sda line is only allowed to change during the time the scl line is low (points 2, 3, 4, 5). after the start information (point 1) the sen line returns to the high level and remains uncharged for all the time the transmission is performed. byte fornat every byte transferred on the sda line must con- tain 8 bits. each byte must be followed by an ac- knowledge bit. the msb is transferred first. acknowledge the master ( m p) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 17). the peripheral (audioprocessor) that acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock. figure 16: timing diagram of s-bus and i 2 cbus tda7310 10/15
application information (continued) the audioprocessor which has been addressed has to generate an acknowledge after the recep- tion of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can gen- erate the stop information in order to abort the transfer. transmission without acknowledge avoiding to detect the acknowledge of the audio- processor, the m p can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking and decreases the noise immunity. interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the tda7310 address (the 8th bit of the byte must be 0). the tda7310 must always acknowledge at the end of each transmitted byte. a sequence of data (n-bytes + acknowledge) a stop condition (p) software specification chip address 1 msb 00010a0 lsb a = logic level on pin addr data bytes msb lsb function 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 b2 0 1 0 1 0 1 1 b1 b1 b1 b1 b1 g1 0 1 b0 b0 b0 b0 b0 g0 c3 c3 a2 a2 a2 a2 a2 s2 c2 c2 a1 a1 a1 a1 a1 s1 c1 c1 a0 a0 a0 a0 a0 s0 c0 c0 volume control speaker att lr speaker att rr speaker att lf speaker att rf audio switch bass control treble control ax = 1.25db steps; bx = 10db steps; cx = 2db steps; gx = 6.25db steps status after power on reset volume speaker audio switch bass treble gain -77.5db -37.5db stereo 5 +2db +2db 0db tda7310 address msb first byte lsb msb lsb msb lsb s100010a0 ack data ack data ack p data transferred (n-bytes + acknowledge) ack = acknowledge s = start p = stop max clock speed 100kbits/s tda7310 11/15
software specification (continued) data bytes (detailed description) volume msb lsb function 0 0 b2 b1 b0 a2 a1 a0 volume 1.25db steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 0 b2 b1 b0 a2 a1 a0 volume 10db steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -10 -20 -30 -40 -50 -60 -70 for example a volume of -45db is given by: 0 0 1 0 0 1 0 0 speaker attenuators msb lsb function 1 1 1 1 0 0 1 1 0 1 0 1 b1 b1 b1 b1 b0 b0 b0 b0 a2 a2 a2 a2 a1 a1 a1 a1 a0 a0 a0 a0 speaker lf speaker rf speaker lr speaker rr 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 0 1 1 0 1 0 1 0 -10 -20 -30 11111 mute for example attenuation of 25db on speaker rf is given by: 1 0 1 1 0 1 0 0 tda7310 12/15
audio switch msb lsb function 0 1 0 g1 g0 s2 s1 s0 audio switch 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 stereo 1 stereo 2 stereo 3 stereo 4 stereo 5 not allowed not allowed not allowed 0 0 1 1 0 1 0 1 +18.75db +12.5db +6.25db 0db for example to select the stereo 2 input with a gain of +12.5db the 8bit string is: 0 1 0 0 1 0 0 1 bass and treble 0 0 1 1 1 1 0 1 c3 c3 c2 c2 c1 c1 c0 c0 bass treble 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 c3 = sign for example bass at -10db is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0 purchase of i 2 c components from stmicroelectronics, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. tda7310 13/15
pqfp44 (10 x 10) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e3 d3 e1 e d1 d e 1 k b pqfp44 l l1 0.10mm .004 dim. mm inch min. typ. max. min. typ. max. a 2.45 0.096 a1 0.25 0.010 a2 1.95 2.00 2.10 0.077 0.079 0.083 b 0.30 0.45 0.012 0.018 c 0.13 0.23 0.005 0.009 d 12.95 13.20 13.45 0.51 0.52 0.53 d1 9.90 10.00 10.10 0.390 0.394 0.398 d3 8.00 0.315 e 0.80 0.031 e 12.95 13.20 13.45 0.510 0.520 0.530 e1 9.90 10.00 10.10 0.390 0.394 0.398 e3 8.00 0.315 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k0 (min.), 7 (max.) outline and mechanical data tda7310 14/15
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com tda7310 15/15

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